The present invention relates to an output driver for a CMOS integrated circuit, and more particularly to such a driver that has reduced susceptibility to ground bounce and electromagnetic interference.
In CMOS integrated circuits, there is a class of circuits known as gate arrays. Gate arrays are manufactured on a substrate containing all of the diffusion regions required for the device. These diffusion regions form transistors, mostly field effects transistors (FETs), that are arranged in arrays. The design process consists of interconnecting individual FETs and groups of FETs into binary gates that provide the desired binary functions. Since CMOS is a high density technology, very complex functions may be realized. Further, there are logic design languages and software that allows the designer to quickly and cost effectively fulfill binary circuit functions using CMOS gate arrays.
As often happens, the functions performed by a gate array integrated circuit are connected to a transistor-transistor logic (TTL) circuit. Thus, the output drivers of a gate array circuit should be capable of driving a TTL input by sufficiently sourcing and sinking current to drive the TTL input and charge the conductor connecting the CMOS output to the TTL input. The standard design of a CMOS output driver to meet the TTL drive specifications results in a CMOS output driver that will draw several times the specified current at output voltages between one and two volts. This excessive current causes noise problems in the CMOS gate array output driver circuit, in the TTL input circuit and in the system that both circuits are part of. This type of noise is referred to as ground bounce for noise on the low voltage side of the power bus of the gate array integrated circuit and power supply noise for the high voltage side of the power bus.
These noise problems are related to the fact that multiple output drivers draw current through one or more common pins connecting the gate array with the high side and low side of the system power supply. One previous solution has been to increase the number of power supply pins per gate array integrated circuit. There is an economic limit to such an approach, however, because for every pin of a package that is used for power supply connection, there is one less pin available to carry a logic signal into or out of the integrated circuit for logic processing. Thus, as long as there are less than two power supply pins for each binary output pin, there will be some of this type of noise problem.
Another solution to the ground bounce and power supply noise problem is to dynamically limit the current that is sourced or sunk by the output driver circuits. Known dynamic limiting circuits are sensitive to circuit parameters such as supply voltage level, transistor transconductance and the bulk resistivity of poly-silicon or single crystal silicon. Such circuits may work satisfactorily at specific supply voltages or load types, but they do not work well over a broad range of temperatures, power supply voltages, load, and manufacturing process variations that gate arrays are subject to.
It is an object of the present invention to provide a constant current output driver.
It is another object of the present invention to provide such an output driver that rapidly switches through the high current drawing portion of its operating curve and thereby limit the amount of current drawn and ground bounce/power supply noise generated.